PLL (Phase-locked loop)

• Phase-locked loop    
• A phase-locked loop or phase lock loop (PLL) is a control system that generates an output signal whose phase is related to the phase of an input "reference" signal. It is an electronic circuit consisting of a variable frequency oscillator and a phase detector. This circuit compares the phase of the input signal with the phase of the signal derived from its output oscillator and adjusts the frequency of its oscillator to keep the phases matched. The signal from the phase detector is used to control the oscillator in a feedback loop.
• Frequency is the derivative of phase. Keeping the input and output phase in lock step implies keeping the input and output frequencies in lock step. Consequently, a phase-locked loop can track an input frequency, or it can generate a frequency that is a multiple of the input frequency. The former property is used for demodulation, and the latter property is used for indirect frequency synthesis.

• 目前此 case 的設計:
• 1. Most internal clocks originate with a 27MHz off-chip crystal.
• 2. The system contains two, on-chip spread-spectrum phase-locked loops (SSPLLs) which use the 27MHz crystal oscillator clock as their input.
• 3. Referring to Figure, PLL0 rate multiplies the 27MHz reference clock up to 1350MHz, and only the primary output of PLL0 is used. This 1350MHz output is used by the main system clock generator (cpu_clkgen).
• 4. We can set the frequency of other device by dividing the primary output of PLL0/PLL1. Example, we set sdmmcclk to 100MHz and sd0clk to 50MHz and observe the frequency with scope after mapping the frequency to GPIO.

•  Program. 當我們設定好 PLL0 時及相關的周邊倍頻 clock 時，依文件提及，可以將欲觀察的 device's clock mapping 到某二根 GPIO 觀察。以下為我測試的步驟。
1. 設定 PLL0 (Regs: PLL0_CR0/PLL0_CR1/PLL0_CR2/PLL0_CR3/PLL0_SR)。這些值的設定主要還是來自原廠的提供，因為沒有相關的 Spec 可查)
2. Enable Clock Gate (Regs: CGCR)。The Clock Gate Control Register allows various clocks inside the ASIC to be powered down under firmware control, to save power when the parts of the ASIC that use them are not in use。所以在測試時，我先將全部的 clock output 全打開。
3. 將要觀查的 device frequency map to GPIO (Regs: CDCR1)。文中提及，會將欲觀察的 frequency map to GPIOB[31:30]，且必需先將此二pin GPIOB[31:30] 設為 AltFun7，再將要觀察的 device frequency 填相對應的值至 CDCR1 中。
4. 測試過程
• evb gate_on // Enable all clock gate
• evb pll0_set // Set PLL0
• evb pll1_set // Set PLL1
• evb io_out val // Set GPIOB[31:30] to AltFunc7 and the related value to CDCR1 to observe  the device's frequency